Electronic devices are generally integrated in a composite chip of semiconductor material; the chip includes a substrate defining a mechanical support for an active layer (typically including one or more epitaxial layers), which active layer houses different electronic components of the device (such as MOSFET transistors); sometimes, one or more (highly doped) buried layers are also enclosed between the substrate and the active layer, or within the active layer (between a pair of adjacent epitaxial layers).
Usually, it is desired to contact the substrate or the buried layers (hereinafter generically denoted as covered layers) with a very low resistance path, in order to collect undesired or functional currents that are injected into them by the electronic components of the device during its operation. Indeed, the undesired currents can adversely affect the device or even destroy it if not suitably discharged; on the other hand, the functional currents would generate large voltage drop and power dissipation if collected through a too high resistance path.
For this purpose, front-side deep contact elements (or simply deep contacts), also referred to as sinkers, may be used. Each deep contact includes a low resistance region (of the same type of conductivity of the covered layer), which extends in the active layer from a front surface of the chip down to the covered layer. For example, these deep contacts are required when it is not possible to collect the currents being injected towards the substrate directly through a backside contact—such as when the device has a poor backside contact or it is assembled with a flip-chip technique.
Alternatively, the same deep contacts may be exploited to insulate corresponding wells of the active layer. In this case, the active layer is of the opposite type of conductivity of the substrate; each deep contact includes a frame of the same type of conductivity of the substrate, which surrounds the well down to the substrate (so as to define an insulation region for the well). As a result, it is possible to insulate the well from the rest of the chip when a P-N junction formed between the insulation region and the well is reverse biased.
Particularly, in medium or high-voltage applications (typically working at 40-150 V and 150-1,000 V, respectively), the active layer is relatively thick (such as 8-12 μm); for example, this is required to implement vertical power components (such as MOS transistors with full vertical gate and current collection structure or with vertical current collection and lateral gate structure). Therefore, in order to reach the covered layer the deep contacts extend very far away from the front surface of the chip.
The above-mentioned deep contacts are obtained by diffusing (i.e., driving-in) doping impurities, or dopant—of the same type of conductivity of the covered layer—within the active layer up to reach the covered layer. Alternatively, it is possible to diffuse doping impurities previously implanted within the covered layer before the formation of the active layer.
A drawback of the solution described above is that the deep contacts so obtained waste a significant area of the device. Indeed, each diffused region has a width (parallel to the front surface of the chip), which increases with its depth, since the doping impurities diffuse approximately uniformly in every direction.
Moreover, in smart power applications the same device also comprises other components, such as logic circuits controlling the power components (for example, a microprocessor and a digital signal processor), a memory module, power supply management circuits and circuits that enable the communication of the device with the outside. All the components of these devices may be manufactured by means of so-called “cold” processes, wherein the doped regions exploited for implementing the electronic components are formed without any diffusion of the doping impurities in the active layer; conversely, short thermal processes (such as annealing processes) are used for activating the doping impurities, which have been previously implanted. However, the cold processes only allow obtaining regions with reduced depths (at most of 4 μm); therefore, they are often unsuitable to form the required deep contacts, which should reach covered layers more far away from the front surface of the chip (such as 8-12 μm).
Different techniques for forming generic low resistance paths are also known in the art.
For example, U.S. Pat. No. 5,188,971, which is incorporated by reference, discloses a sinker, which is self-aligned with an insulating trench of a bipolar device. The sinker includes a heavily doped region used for connecting a collector region of the transistor to the substrate. In order to form the sinker, doping impurities are diffused around a region where the trench is partially formed; the trench is then completely etched down to the substrate and it is finally filled with insulating material (such as silicon oxide).
U.S. Pat. No. 4,939,567, which is incorporated by reference, discloses a horizontal contact between a P-type diffused region and an N-type diffused region implementing a source region of a P-MOS transistor and a drain region of an N-MOS transistor, respectively (for a SRAM memory cell). The horizontal contact includes a trench arranged between the two diffused regions; the trench is coated with a thin conforming insulating layer and then filled with conductive material, which electrically couples the two regions.
U.S. Pat. No. 5,891,776, which is incorporated by reference, discloses a method to form an IGBT (Insulated Gate Bipolar Transistor). In particular, the formation of the doped regions (being exploited for implementing the IGBT) is achieved by depositing or implanting doping impurities through a trench extending into a stack of semiconductor layers and then diffusing the doping impurities into the semiconductor region surrounding the trench. The trench is now covered with an insulating layer, and it is filled with conductive material (such as aluminum).
More generally, the trenches are also used in different applications.
For example, U.S. Pat. No. 5,488,236, which is incorporated by reference, discloses a gate controlled bipolar transistor with a gate electrode that is formed in a trench.
Finally, in U.S. Pat. No. 6,956,266, which is incorporated by reference, the trenches, which are coated with an insulating conforming layer and filled with polysilicon, are used for suppressing the latch-up in integrated circuits.